5a - For the Maste-Slave D-latch configuration given below, complete the timing diagram - Master Slave Om D Q D Q Clk Q Clk Q Clock 5b - Draw intermediate output Qm and final output Q-Qs values in the timing diagram below for each clock cycle shown - : t0 :t1 : t4 : t5 : clock 5c - Does this device as a whole behave like a positive-edge flip-flop or negative-edge flip-flop? Briefly explain why