6. [1506] We have a computer system with two levels of caches. The LI caches are separate instruction and data caches (LITS and LIDS), while the L2 cache is a unified cache (UL2$). The ideal CPI (no cache miss) for this computer is 2. On the average during runtime, 25% of the instructions are load/store. The miss rates for LIIS and LIDS are 8% and 10%, respectively. The UL2S has a global miss rate 1%. When LI caches miss but L2 cache hits, it takes 30 extra cycles. When both LI and L2 miss, it takes 200 extra 7. Assume that each memory address of a computer system can address up to SG bytes. The memory location is byte addressed. Suppose we use a 64K-byte cache to improve the performance. The cache is organized in a way that each block consists of 32 bytes. (a) [656] Suppose the cache is direct mapped. Which bit fields of the address indicate the tag, the cache index, and the offset, respectively? (b) [6%] Suppose the cache is fully associative. Which bit fields of the address indicate the tag and the offset, respectively? (c) [6%] Suppose the cache is 4-way set associative. Which bit fields of the address indicate the tag, the cache index, and the offset, respectively