6. (30 points) Enter T(for true), or leave blank for false, to indicate whether each statement below is true or false. On ZYNQ, all 32 bits of the ARM address bus are brought off-chip to address external memory One gigabyte of DDR is included as an IP block on the ZYNQ chip In a RISC machine, one ALU operand must come from a register, and one can come from external memory You can write an ARM shift instruction that will not execute if the previous result was negative An ARM branch instruction target address can be anywhere in the entire 29 address space In a two-address machine, one operand location must also serve as the destination Six bits in the lower word of an ARM instruction define conditional execution settings for the instruction The "S" bit in the ARM opcode is used to determine whether a conditional instruction is executed The ARM has 16 registers, but only 13 of them are typically used for general data storage The link register cannot be modified by ARM instructions ARM defines an ascending stack All ARM opcodes set aside 12 bits to be used for immediate values In ARM, the AMBA bus is used to connect peripheral IP blocks to the processor By ARM convention, the stack pointer uses register R13 By ARM convention, RO-RS are designated for parameter passing If R1 = 0x000000FF, after the instruction "AND RO, R1, R2", the largest number that could be in RO is 255 Cache memory access is typically faster than main memory access ALU status bits can be inspected to determine the result of the next-to-be-executed instruction The ARM calling conventions call for RO-R13 to be saved and restored during any context switch The stack is stored in a special memory area that cannot be overwritten by user programs User programs can read the CPSR to check CPU status, and write CPSR to change modes