$6.$ A many$-$input OR gate as shown in Fig.$($a$)$ is usually implemented by a pseud$-$nMOS NOR gate A followed by a CMOS inverter B as Fig.$($b$).$ The voltage division ratio of the pseudo$-$nMOS is set to $\backslash (4$: $1\backslash )$ then the characteristic curves of the pseudonMOS and CMOS gates can be approximated as Fig. $($c$)$ and $($d$)$ respectively. Based on the maximum$-$static$-$noise$-$margin $($SNM$)$ and minimum$-$area criteria, decide the transistor sizes of the two primitive gates A and B$.$

$($a$)$

$($b$)$

$($d$)\backslash (\backslash$quad V $\backslash )$