6. Consider a memory system with the following parameters Translation Look aside Buffer has 512 entries and is 2-way set associative. 64Kbyte L1 Data Cache has 128 byte lines and is also 2-way set associative. Virtual addresses are 64-bits and physical addresses are 32 bits 8KB page size are diagrams of the cache and TLB. Please fill in the appropriate information in the table that follows the diagrams Below assume 2 for status bits) Cache Phys. Addr Tagl Tag Data Daa Compare Compare TLB Virtual Addr Tag! Tag Status Data Status Daa Compare Compare