$6)$ Construct a $4-$input NAND gate in the following logic families: a$)$ Static CMOS Logic b$)$ Pseudo$-$NMOS Logic$*$ c$)$ Footed Dynamic Logic$**$ In each case, properly size all transistors such that the worst$-$case ON resistance of the devised circuits is equal to that of a minimum$-$sized static CMOS inverter assuming n$=2$p$,$ and calculate the up$/$down logical effort $($gu$,$ gd$)$ for every input and up$/$down parasitic delay $($pu$,$ pd$)$ for the input closest to the output. Hints: $*$ In typical Pseudo logic circuits, the pull$-$down network ON$-$resistance should be equal to that of a minimum$-$sized static CMOS inverter and pull$-$up network should have four times less current capability than the pull$-$down network. $**$ In typical dynamic logic circuits, the pull$-$down network ON$-$resistance should be equal to that of a minimum$-$sized static CMOS inverter and pull$-$up transistors should be unit sized. $6)$ Construct a $4-$input NAND gate in the following logic families:

a$)$ Static CMOS Logic

b$)$ Pseudo$-$NMOS Logic$*$

c$)$ Footed Dynamic Logic$**$

In each case, properly size all transistors such that the worst$-$case ON resistance of the devised circuits is equal to that of a minimum$-$sized static CMOS inverter assuming $\backslash (\backslash$mu$\_\{\backslash$mathrm$\{$n$\}\}=2\backslash$mu$\_\{\backslash$mathrm$\{$p$\}\}\backslash ),$ and calculate the up$/$down logical effort $\backslash (\backslash$left$(\backslash$mathrm$\{$g$\}\_\{$u$\},\backslash$mathrm$\{$~g$\}\_\{\backslash$mathrm$\{$d$\}\}\backslash$right$)\backslash )$ for every input and up$/$down parasitic delay $\backslash (\backslash$left$(\backslash$mathrm$\{$p$\}\_\{$u$\},\backslash$mathrm$\{$p$\}\_\{\backslash$mathrm$\{$d$\}\}\backslash$right$)\backslash )$ for the input closest to the output.

Hints:

$*$ In typical Pseudo logic circuits, the pull$-$down network ON$-$resistance should be equal to that of a minimum$-$sized static CMOS inverter and pull$-$up network should have four times less current capability than the pull$-$down network.

$**$ In typical dynamic logic circuits, the pull$-$down network ON$-$resistance should be equal to that of a minimum$-$sized static CMOS inverter and pull$-$up transistors should be unit sized.