6.9 Consider the following three CPU organizations: CPU SS: A two-core superscalar microprocessor that provides out-of-order issue capabilities on two function units (FUs). Only a single thread can run on each core at a time. CPU MT: A fine-grained multithreaded processor that allows instructions from two threads to be run concurrently (i.e., there are two functional units), though only instructions from a single thread can be issued on any cycle. CPU SMT: An SMT processor that allows instructions from two threads to be run concurrently (i.e., there are two functional units), and instructions from either or both threads can be issued to run on any cycle Assume we have two threads X and Y to run on these CPUs that 1126 include the following operations Thread X Thread Y Al-takes three cycles to execute B1-take two cycles to necute A2 - no dependences B2-conflicts for a functional unit with BI A3 --conflicts for a functional unit with 33 - depends on the result of 2 AL A4-depends on the result of 13 B4 - no dependences and takes two cycles to Cute Assume all instructions take a single cycle to execute unless noted otherwise or they encounter a hazard 6.9.1 [10] Assume that you have one SS CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 6.9.2[10] Now assume you have two SS CPUs. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 6.9.3 [10] Assume that you have one MT CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 6.9.4 [10] Assume you have one SMT CPU. How many cycles will it take to execute the two threads? How many issue slots are wasted due to hazards