7. We assume a hypothetical CPU architecture which utilizes a paging-based memory management. The CPU is an 8-bit architecture, however if offers only a 6-bit virtual address space and supports only 6-bit physical addresses. The address format of the architecture is shown below 6-bit virtual address 2 Page Page Page 2 2 directory table offset (PD) (PT) Each page directory entry and page table entry is 8-bit long and has the following format 4 bit frame number valid write reseved reserved alid 0: not valid rite 0: no write allowed : write allowed Suppose the operating system just created the two processes whose address spaces are shown in the following figure. The left part of the figure shows the two virtual address spaces. The right part shows how the virtual pages are allocated to physical frames. PD 1 denotes the page directory table for the first process, PD 2 is the page directory for the second process. PT ij refers to the j-th page table used by proecess i. For example, PT 2,1 is the first page table used by process 2) 7. We assume a hypothetical CPU architecture which utilizes a paging-based memory management. The CPU is an 8-bit architecture, however if offers only a 6-bit virtual address space and supports only 6-bit physical addresses. The address format of the architecture is shown below 6-bit virtual address 2 Page Page Page 2 2 directory table offset (PD) (PT) Each page directory entry and page table entry is 8-bit long and has the following format 4 bit frame number valid write reseved reserved alid 0: not valid rite 0: no write allowed : write allowed Suppose the operating system just created the two processes whose address spaces are shown in the following figure. The left part of the figure shows the two virtual address spaces. The right part shows how the virtual pages are allocated to physical frames. PD 1 denotes the page directory table for the first process, PD 2 is the page directory for the second process. PT ij refers to the j-th page table used by proecess i. For example, PT 2,1 is the first page table used by process 2)