7.1 Consider an arithmetic circuit that can perform four operations: a+b, a-b, a+1 and a-1, where a and b are 16-bit unsigned numbers and the desired operation is specified by a 2-bit control signal, ctrl. (a) Design the circuit using two adders, one incrementor and one decrementor. Derive the VHDL code. (b) Design the circuit using only one adder. Derive the VHDL code. (c) Synthesize the two designs with an ASIC device. Compare the areas and perfor- mances. (d) Synthesize the two designs with an FPGA device. Compare the areas and perfor- mances. 7.1 Consider an arithmetic circuit that can perform four operations: a+b, a-b, a+1 and a-1, where a and b are 16-bit unsigned numbers and the desired operation is specified by a 2-bit control signal, ctrl. (a) Design the circuit using two adders, one incrementor and one decrementor. Derive the VHDL code. (b) Design the circuit using only one adder. Derive the VHDL code. (c) Synthesize the two designs with an ASIC device. Compare the areas and perfor- mances. (d) Synthesize the two designs with an FPGA device. Compare the areas and perfor- mances