7.Tightly coupled multiprocessor systems

Select one:

a. Share a common memory and the same set of I/O devices

b. Share different memories and different set of I/O devices

c. Share a common memory and different set of I/O devices

d. None of the mentioned

8.

The ways in which I/Os can be controlled are

Select one:

a. Programmed I/O, Interrupt-Driven I/O, Direct Memory Access, and Channel I/O.

b. Programmed I/O, Interrupt-Driven I/O, Memory-Mapped I/O, Direct Memory Access, and Channel I/O.

c. Programmed I/O, Memory-Mapped I/O, Direct Memory Access, and Channel I/O.

d. Programmed I/O, Interrupt-Driven I/O, Memory-Mapped I/O, and Channel I/O.

9.

RISC have, amongst other specifications,

Select one:

a. Single-cycle instructions, fixed length instructions, with few addressing modes.

b. Single-cycle instructions, fixed length instructions, microprogrammed control, with few addressing modes.

c. Single-cycle instructions, variable length instructions, with few addressing modes.

d. Single-cycle instructions, fixed length instructions, parameter passing through memory, with few addressing modes.

10.

Embedded systems programmers need not understand every detail about the hardware

Select one:

True

False

11.

In a computer environment, slow I/O device(s) will impact system performance due to a so-called ripple effect

Select one:

True

False

12.

I/O subsystems comprise of

Select one:

a. Blocks of main memory, buses, and special interpreter

b. Blocks of main memory, buses, interfaces and special cabling

c. Blocks of main memory, buses, and special compiler

d. Blocks of main memory, buses, and special cabling

13.

SRAM is a very fast memory and it doesnt need to be refreshed like DRAM does.

Select one:

True

False

14.

Superscalar architectures include a single execution unit such as specialized integer and floating-point adders and multipliers.

Select one:

True

False

15.

Parallel processing is capable of economically increasing system throughput while providing better fault tolerance

Select one:

True

False

16.

A serial data transmission link uses

Select one:

a. Two wires

b. Eight wires

c. Nine wires

d. One wire

17.

In content addressable cache memory, a subset of the bits of the main memory address called fields are organized as

Select one:

a. Tag, Block and offset fields

b. Set, Tag, Flag, Block, and offset fields

c. Set, Tag, and offset fields

d. Set, Tag, Block, and offset fields

18.

For the software in embedded systems, memory limitations are almost always a software development constraint and this is due to lack of input and output memory mapping

Select one:

True

False

19.

Effective Access Time is calculated using

Select one:

a. Acces times, hit rates, miss rates, and miss penalties.

b. Acces times, hit rates, and miss rates.

c. Hit rates, miss rates, and miss penalties.

d. Acces times, hit rates, and miss penalties.

20.

Virtual memory uses

Select one:

a. Part of main memory and all of the hard drive

b. Part of main memory and none of the hard drive

c. Part of main memory and part of the hard drive

d. No part of main memory and all of the hard drive