(8 pts) Using the module definitions from Problem 1 (4-bit ripple carry adder) and Problem 6 (Figure 3-33), implement the arithmetic circuit shown in the Case Study 2 Sample Solution. You will need to instantiate the ripple carry adder module and as many muxes as you need into your Verilog model. Compile and simulate the circuit in Quartus. Submit the waveform showing all inputs and outputs. Use the following inputs R1Ro Co 0 00 01 01 10 10 ? 0 1 0 1 0 0100 1101 (8 pts) Using the module definitions from Problem 1 (4-bit ripple carry adder) and Problem 6 (Figure 3-33), implement the arithmetic circuit shown in the Case Study 2 Sample Solution. You will need to instantiate the ripple carry adder module and as many muxes as you need into your Verilog model. Compile and simulate the circuit in Quartus. Submit the waveform showing all inputs and outputs. Use the following inputs R1Ro Co 0 00 01 01 10 10 ? 0 1 0 1 0 0100 1101