(9 points) Assuming that someone has prepared a Verilog design of a 4 bit universal shift register. Show how you can test his/her design and verify that it is functional.

the module is declared as follows:

module Shift_Reg (

output reg [3: 0] A_par,

input [3: 0] I_par,

input s1, s0,

MSB_in, LSB_in, CLK, Clear_b);

A_par s1 so 4 MSB_in Shift_Register LSB_in CLK Clear_b 14 l_par