X ADVANCED DIGITAL SYSTEM SaHI X 02 (8 points) ... AAUP E-learning - Moodle English (en) Question 1 (9 points) Assuming that someone has prepared a Verilog design of a 4 bit universal shift register. Show how you can test his/her design and verify that it is functional. Not yet answered the module is declared as follows: Marked out of 6.00 P Flag question module Shift_Reg output reg [3:0] A_par, input [3:0] lpar, input s1, so MSB_in, LSB_in, CLK, Clear_b); A_par s/ s0 MSB in Shift_Register L.SB in 4 CLK Clearb Lpar Mode Control si So Register Operation 0 0 0 1 No change Shift right Shift lett Parallel load 1 0 1 1