Question: ( a ) ( 1 pt ) Determine A , B , and C to maximize the clock frequency if the circuit has positive clock

(a)(1 pt) Determine A, B, and C to maximize the clock frequency if the circuit has positive clock skew and find that clock frequency. Assume all the D-FF setup, hold and c to q times are all zero. Now assume A =0.2ns,B =0.1ns, and C =0.3ns and the setup, hold, and tcq times are as given. (b)(1 pt) What is Tmin for Clk2 being fed from the right? (c)(1 pt) What is Tmin for Clk1 being fed from the left? (d)(1 pt) What is Tmin for both clocks if A =B =C =0ns?(e)(1 pt) If the clock has a worst-case jitter of 0.05ns, how should the Tmin in (b) be adjusted?

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