In the circuit shown below, setup time and hold time of a flipflop are $20$ ps $.$ CLK$-$to$-$Q delay of a flipflop is $1020ps.$ Clock jitter is $5ps.R=10\frac{}{},$ wire thickness $=10nm,$ wire length $=100m,$ wire width $=5m.$ Wire capacitance is $0\mathrm{.}1f\frac{F}{}m$ when the width of wire is $1m.$ All the input capacitance of flipflops are $450$ fF $,$ but there are no output capacitance of flipflops. minimum length of the $\frac{P}{N}$MOS is $0\mathrm{.}1m.$ An unit size NMOS $($width$=0\mathrm{.}1m,$ length $=0\mathrm{.}1m)$ has resistance of $100$ and $C_g=C_s=C_d=10fF.$ Use lumped model when you calculate the wire delay. Use Elmore delay when you calculate delays. The signal path from R $1$ to R $2$ is the critical path, and it is connected to the inner input. Assume non$-$critical paths are arrived much earlier than critical path. ${}_p$:${}_n=1$:$2$

a$)$ Determine the size $($W&L$)$ of $2-$input NOR and $3-$input NAND gate above by following guidelines below. $(10$ pts $)$

Rising and falling delay must be identical in the worst case.

Achieve minimum propagation delay.

Size of pull down NMOSs of the first stage $2-$input NOR gate is $\frac{W}{L}=0\mathrm{.}1\frac{m}{0\mathrm{.}1}m.$

b$)$ Calculate contamination and propagation delay of combinational logic $($total delay, $2-$input NOR delay $+3-$input NAND$)(10$ pts$).$

c$)$ If the clock frequency is $10$ GHz $,$ show setup time constraints. $(5$ pts$)$

d$)$ If the clock frequency is $10$ GHz $,$ show hold time constraints. $(5$ pts $)$

e$)$ If we have an ideal delay cell which provide fine$-$controlled fixed delay, calculate the minimum clock period and the delay of the ideal delay cell which satisfy both setup and hold time constraint. $(10$ pts$)$

f$)$ Explain pros and cons when you choose either CLK$1$ or CLK$2$ as a clock input $($considering hold$/$setup time constraints$).$ No more than $4$ sentences are allowed. More than $4$ sentences will deduct the score. $(10$ pts$)$