A 32-bit processor has the following four 32-bit instruction formats. "IntReg" means a general purpose register. "FPReg" means a register that connects only to the floating point arithmetic circuits of the ALU. "2's comp" means that the field uses a 2's complement representation Format Number 5-bit field 5-bit field 5-bit field 5-bit field 12-bit field Opcode IntRe Opcode FPReg A FPReg BFPReg C Unused g A IntReg B IntReg CUnused 3 |Opcode | ntReg A Unused PReg CUnused 5-bit field5-bit field5-bit field 1-bit field 16-bit field 4OpcodeIntReg A IntReg B UnusedImmediate (2's com Answer Questions 1 through 6 given the above information. 1. How many general purpose registers does this processor have? What is the capacity of 2. 3. 4. each of these registers? How many floating-point registers does this processor have? Up to how many machine language instructions does this processor have? Which instruction format will be used to perform an integer ADD instruction? Answer by giving the number of the format. Which format will be used to perform a STORE instruction? If the register used for the base address of the assembly language instruction 5. 6. STORE R16, Offset(R19) contains 0xABCD0000 and the offset has the maximum positive value that will write to an aligned word, what is the byte address that the STORE sends to the L1 data cache? A 32-bit processor has the following four 32-bit instruction formats. "IntReg" means a general purpose register. "FPReg" means a register that connects only to the floating point arithmetic circuits of the ALU. "2's comp" means that the field uses a 2's complement representation Format Number 5-bit field 5-bit field 5-bit field 5-bit field 12-bit field Opcode IntRe Opcode FPReg A FPReg BFPReg C Unused g A IntReg B IntReg CUnused 3 |Opcode | ntReg A Unused PReg CUnused 5-bit field5-bit field5-bit field 1-bit field 16-bit field 4OpcodeIntReg A IntReg B UnusedImmediate (2's com Answer Questions 1 through 6 given the above information. 1. How many general purpose registers does this processor have? What is the capacity of 2. 3. 4. each of these registers? How many floating-point registers does this processor have? Up to how many machine language instructions does this processor have? Which instruction format will be used to perform an integer ADD instruction? Answer by giving the number of the format. Which format will be used to perform a STORE instruction? If the register used for the base address of the assembly language instruction 5. 6. STORE R16, Offset(R19) contains 0xABCD0000 and the offset has the maximum positive value that will write to an aligned word, what is the byte address that the STORE sends to the L1 data cache