A 5-bit counter circuit with forward counting operation with comparison feature will be designed. The circuit will also have parallel load and CE (Clock Enable) inputs. Block diagram of the circuit Figure It is given in 1. The circuit to be designed should provide the state table given in Table 1. Realize the design of this logic circuit. 1 When logic-0 is given to the preset input, the counter outputs should be 11111. When PY (Parallel Loading) control input is logic "1", values in Data" inputs will be transferred to Qoutputs. If the CE input is logic-0, the counter outputs will remain the same. When the CE entry is made as logic-1, counting should be done according to the result of the comparison process. If the counter value is greater than (7 +9), a forward counting operation should be performed one by one. Otherwise, counting must be done by twos. Data Q Preset PY CE Tablo 1. Sayc devresinin durum tablosu Preset PYCE Q(n+1) 0 1 1 1 X Data 1 0 Qan) 1 1 If Q(n)>7+9) then Q(n)+1 Otherwise Q(n)+2 Xolo Based on the input and output terminals defined here, design the inside of the block and draw the detailed circuit diagram. **** Design the circuit in accordance with the GAL22V10 ****