A 6T SRAM cell is fabricated in a 0.13-um CMOS process for which Dp = 1.2...

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A 6T SRAM cell is fabricated in a 0.13-um CMOS process for which Dp = 1.2 V, V, = 0.4 V, and H,Cor = 430 uA/V*. The inverters utilize (WIL), = 1. Each of the bit lines has a 2-pF capacitance to ground, The sense amplifier requires a minimum of 0.2-V input for reli- able and fast operation. %3D %3! (a) Find the upper bound on WIL for each of the access transistors so that Vo and Vz do not change by more than V, volts during the read operation. (b) Find the delay time Af encountered in the read operation if the cell design utilizes minimum-size access transistors. (c) Find the delay time At if the design utilizes the maxi- mum allowable size for the access transistors. A 6T SRAM cell is fabricated in a 0.13-um CMOS process for which Dp = 1.2 V, V, = 0.4 V, and H,Cor = 430 uA/V*. The inverters utilize (WIL), = 1. Each of the bit lines has a 2-pF capacitance to ground, The sense amplifier requires a minimum of 0.2-V input for reli- able and fast operation. %3D %3! (a) Find the upper bound on WIL for each of the access transistors so that Vo and Vz do not change by more than V, volts during the read operation. (b) Find the delay time Af encountered in the read operation if the cell design utilizes minimum-size access transistors. (c) Find the delay time At if the design utilizes the maxi- mum allowable size for the access transistors.