(a) A uniprocessor system uses a separate instruction and data caches with the hit ratios hi...

 

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(a) A uniprocessor system uses a separate instruction and data caches with the hit ratios hi and hd, respectively. The access time from the processor to either cache is c clock cycles, and the block is transfer time between the caches and main memory is b block cycles. Among all memory references made by the CPU, fi is the percentage of the references to instructions. Among blocks replaced in the data cache, fdir is the percentage of dirty blocks. Assuming a write-back policy, determine the effective memory access time in terms of hi, hd, c, b, fi, fdir for this memory system. (b) The processor memory system described in part (a) is used to construct a bus-based shared memory multiprocessor. Assume that the hit ratio and access time remain the same as in part (a). However, the effective memory-access time will be different because every processor must now handle cache invalidations in addition to reads and writes. Let finv be the fraction of data references that cause invalidation signals to be sent to other caches. The processor sending the invalidation signal requires i clock cycles to complete the invalidation process. Other processors are not involved in the invalidation (a) A uniprocessor system uses a separate instruction and data caches with the hit ratios hi and hd, respectively. The access time from the processor to either cache is c clock cycles, and the block is transfer time between the caches and main memory is b block cycles. Among all memory references made by the CPU, fi is the percentage of the references to instructions. Among blocks replaced in the data cache, fdir is the percentage of dirty blocks. Assuming a write-back policy, determine the effective memory access time in terms of hi, hd, c, b, fi, fdir for this memory system. (b) The processor memory system described in part (a) is used to construct a bus-based shared memory multiprocessor. Assume that the hit ratio and access time remain the same as in part (a). However, the effective memory-access time will be different because every processor must now handle cache invalidations in addition to reads and writes. Let finv be the fraction of data references that cause invalidation signals to be sent to other caches. The processor sending the invalidation signal requires i clock cycles to complete the invalidation process. Other processors are not involved in the invalidation

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