a. Analyze the VHDL code given below for a Flip flop and

I. Describe the nature of all the inputs, (6 Marks)

II. Obtain the functional table of the flip flop with values of input, clk, pre, clr, Q and Qbar; and (8 Marks)

III. Identify the type of the Flipflop; (1 Marks)

library ieee;

use ieee.std_logic_1164.all;

entity FF is

port (input,clk,pre,clr: in std_logic; Q: buffer std_logic; Qbar: out std_logic);

end entity FF;

architecture behavior of FF is

begin

Process (clk )

begin

if (clkevent and clk=1 )then

if pre= 0 then

Q<= 1;

Elsif clr=1 then

Q<='0';

elsif (input=0) then

Q<=0;

Qbar <= not Q;

elsif (input=1) then

Q<=1;

Qbar<=Q;

end if;

endif;

end process;

end behavior;