a. Analyze the VHDL code given below for a Flip flop and I.Describe the nature of all the inputs, (6 Marks) II. Obtain the functional table of the flip flop with values of 'input', 'clk', 'pre', 'clr', 'Q' and 'Qbar'; and (8 Marks) III. Identify the type of the Flipflop; (1 Marks) library ieee; use ieee.std_logic_1164.all; entity FF is port (input,clk, pre,clr: in std_logic; Q: buffer std_logic; Qbar: out std_logic); end entity FF; architecture behavior of FF is begin Process (clk ) begin if (clk'event and clk='1' )then if pre= 'O' then Q