A cache has lines of 4 bytes each, and there is space for 8 lines, total, in the cache. There are 256 bytes in main memory. How is the memory address broken into fields for each the following cache mapping schemes: (A) direct mapping;(B) associative mapping;(C) 2-way set associative mapping. For each mapping scheme, list all possible locations in the cache for memory address 0x4A (Note: all addresses given in hex. 0x6A = 0b01101010) Consider a loop which accesses the following addresses in order, over and over:

0x1A, 0x1B, 0x5E, 0x5F, 0x0E, 0x0F

Show all line movements between cache and main memory, indicate cache hits and misses. When necessary, assume the LRU replacement algorithm is used.

Indicate the hit ratio for the first iteration of the loop (when initial memory access cause compulsory misses), as well as the hit ratio for subsequent iterations (once the cache has been filled)

You may use a table like this to complete this question:

address	binary	tag	word	operation	cumulative hit ratio
0x6A	0b01101010	011010	00	compulsory miss, load line 011010 into slot 1	0/1 = 0%

BONUS: Show that 3-way set associative cache be an improvement over all three cache schemes in this scenario.