A computer has a CPU with a $0\mathrm{.}25$ ns clock cycle time and a three$-$level cache. The first$-$level cache is a unified $64$ KB$,4-$way associative with a block size of $64$ bytes. The second$-$level cache is a unified $1$ MB$,$ direct mapped with a block size of $512$ bytes. The third$-$level cache is a unified $256$ MB$,$ direct mapped with a block size of $1,024$ bytes.

A hit in the first$-$level cache results in moving the item requested to the CPU in one clock cycle. A miss in the first$-$level cache causes an access to the second$-$level cache which has a $4\mathrm{.}0$ ns access time and a transfer rate of $32$ bytes per $1\mathrm{.}0$ ns$.$ A miss in the second$-$level cache causes access to the third$-$level cache which has a $10\mathrm{.}0$ ns access time and a transfer rate of $64$ bytes per $1\mathrm{.}0$ ns$.$ A miss in the third$-$level cache causes an access to the main memory which has a $40\mathrm{.}0$ ns access time and a transfer rate of $128$ bytes per $1\mathrm{.}0$ ns$.$

The global miss rate of the cache system is $0\mathrm{.}0011748$; the miss rate of the first$-$level cache is $0\mathrm{.}0089$; the local miss rate of the second$-$level cache is $0\mathrm{.}220.$

Determine the average memory access time in CPU cycles.