$*$A computer has the following specifications: a Cache memory of $256$ words. Block size of $16$ words. The main memory $($MM$)$ size is $131072$ words. The cache access time is $1$ns$.$MM access time is $10$ ns$.$ Non$-$Load$-$through read policy. Direct Mapping.

$*$Assume that the cache is initially empty and the CPU fetches memory locations $0$ to $319$ sequentially $5$ times.

a$)$ How many bits are needed for the main memory address bus?

b$)$ How many cache blocks?

c$)$ How many bits are allocated as "TAG" in main memory address?

d$)$ How many unique MM blocks will be mapped to a particular cache block?

e$)$ How long will the CPU fetch those memory locations, assuming NO cache memory $($in ns$)?$

f$)$ During the $1$st pass, how many MM blocks are cache miss?

g$)$ During the $2$nd pass, how many MM blocks are cache miss?

h$)$ During the $3$rd pass, how many MM blocks are cache miss?

i$)$ Overall, how many MM blocks are cache hit?

j$)$ Overall, how many MM blocks are cache miss?