Prolem3: Consider a memory system with a two-level hierarchy with a cache M1 and main memory M2. Size of the main memory, M2 is 256 bytes with block size of 16 bytes. Size of the cache, M1 is 64 bytes with the same block size of 16 bytes. The word length is 4 bytes, implying 4 words per block. A sample trace program generates the following sequence of word addresses: 0,8,1,16,20,21,24,32,61,3,31,19,60,16,11,22,19,8,28,21,42,28,59,58,55 Note, every time a new block is accessed by the cache, up to 4 words are received implying that if block 0 is accessed from the main memory then 0,1,2,3 words are obtained and so on. The addresses given above are word addresses, not memory block addresses.

Consider the same memory system described in Problem 3. However, there is a victim cache V between cache M1 and main memory M2. The size of the victim cache, V is 32 bytes. Assume that both the cache and victim are fully associative with LRU replacement policy. Assume the same sequence of word addresses generated as in Problem 3. At the end of the sequence of words generated, show the state of cache and victim cache. In other words, show what blocks (words) are in cache and what blocks (words) are in victim cache? Assuming that the hit time for the cache is 2 cycles, the hit time for the victim cache is 4 cycles and the hit time for the main memory is 20 cycles, calculate the total number of cycles required to execute the sequence of word addresses. Note that the hit time for victim cache includes the miss penalty for the cache and the hit time for main memory includes miss penalty for the cache and the victim cache.