a$)$ Consider a DRAM based on $1-$Transistor DRAM cell and operating at $\backslash (\backslash$mathrm$\{$V$\}\_\{\backslash$mathrm$\{$OD$\}\}=2\mathrm{.}5\backslash$mathrm$\{$~V$\}\backslash ).$ Threshold voltage of NMOS is $0\mathrm{.}5$ V and pre$-$charge voltage of bit line is $1\mathrm{.}25$ V $.$

Cell storage capacitance is $50$ fF and the bit$-$line capacitance is $1$ pF $.$ How much voltage swing is created on the bit line when a cell storing $\text{'}1\text{'}$ is accessed for the read operation?

b$)$ i$)$ A dynamic memory cell has a worst$-$case leakage current of $2$ nA $($independent of voltage$)$ and is refreshed every $\backslash (100\backslash$mu $5\backslash ).$ If the power supply is $3$ V and the cell

voltage should not leak lower than $1\mathrm{.}8$ V $,$ find the required cell capacitance value.

ii$)$ In a DRAM memory, the sense amplifiers are connected directly to the bit lines. In an SRAM memory, the sense amplifiers are connected to the bit lines through $2$ isolation PMOS transistors. Explain why, the isolation transistors are needed in an SRAM. Also, explain why the isolation transistors should NOT be used in a DRAM.