Question: (a) Consider the Binary Coded Decimal -to- Decimal Decoder (implemented with NAND gate) shown in Figure below. The figure shows the timing for the inputs

(a) Consider the Binary Coded Decimal -to- Decimal Decoder (implemented with NAND gate) shown in Figure below. The figure shows the timing for the inputs (A0, A1, A2, and A3). Draw the timing for the outputs considering the relationship with each other's and with inputs. marks]

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