A CPU implements a stack-based i.e., zero-address) instruction set, where there are four general purpose resisters (RO, R1, R2, and R3), a stack pointer (SP), and a register named (TMP). The stack pointer is a register that holds the memory address of the top element of the stack. The TMP register is used to hold temporary data, e.g. during exchange operations. Every register in that CPU has a dedicated connection with every other register and every ALU input. Write in your answer sheet the sequence of micro-operations (and show the steps) required for that CPU to execute the following instructions: 1. DECREMENT (Decrement the top element of the stack) 2. ADD (Add the values of the top two elements of the stack and store the result back in the stack) 3. POP R1 Question 3: A pipelined processor has the following features: Four pipeline stages: fetch instruction (FI), decode instruction (DI), calculate and fetch memory operands (FO), and execute instruction and store memory operands (EI). Register operands are accessed for read/write) by El stage. Memory ports: one read port and one write port. Branch prediction: based on takenot-taken switch as described in class (assume that we start at not-taken state). Suppose the processor executes the following loop, and assume that the memory location referenced by R1 has a value of 60 (decimal) initially: Instruction No Instruction 11 LOOP: DEC (R1) /* [R1] + [[R1]] - 1 */ JNZ (R1), LOOP /* Jump to LOOP if [[R1]] # 0 */ 13 14 12 15 (a) Draw a timing diagram to show instruction pipelining during the first four iterations of the loop. Make sure you take care of hazards. 6) How many clock cycles are needed to execute this loop until it ends