(a) Determine the logic expressions to implement an address decoding circuit to realize the address map shown below (in hexadecimal notation). Use partial address decoding technique in your design. ROM1 00 0000 00 1FFF ROM2 00 2000 00 3FFF ROM3 00 4000 00 7FFF RAM 04 0000 0F FFFF. [ 4 marks ]

(b) Figure 1 shows the internal memory cells of a 16x4 PROM chip. What data do you need to store in these cells to realise a PROM based implementation of the decoder you designed in Question 3(a)? You must also show the input sources and output destinations of the PROM chip.

3. (a) Determine the logic expressions to implement an address decoding circuit to realize the address map shown below (in hexadecimal notation). Use partial address decoding technique in your design ROM1 00 0000 00 1FFF ROM2 00 2000 00 3FFF ROM3 00 4000-00 7FFF RAM 04 0000- OF FFFF 4 marks ] (b) Figure 1 shows the intemal memory cells of a 16x4 PROM chip. What data do you need to store in these cells to realise a PROM based implementation of the decoder you designed in Question 3(a)? You must also show the inout sources and 3 marks ] RO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 1. Memory cells in a Programmable ROM Chip 3. (a) Determine the logic expressions to implement an address decoding circuit to realize the address map shown below (in hexadecimal notation). Use partial address decoding technique in your design ROM1 00 0000 00 1FFF ROM2 00 2000 00 3FFF ROM3 00 4000-00 7FFF RAM 04 0000- OF FFFF 4 marks ] (b) Figure 1 shows the intemal memory cells of a 16x4 PROM chip. What data do you need to store in these cells to realise a PROM based implementation of the decoder you designed in Question 3(a)? You must also show the inout sources and 3 marks ] RO R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Figure 1. Memory cells in a Programmable ROM Chip