(a) Figures 1 shows a 4-bit unsigned multiplication. Design a 4-bit variable- constant unsigned multiplier where the constant input b = 13. Show all your design steps and draw the logic diagram using the minimum number of components. a2 a1 ao b3 b2b bo azbo a boabo a bo azbab abi aob a3b2a2b2ab2 a,b2 a3b3a2b3 abg abg P P6 PS P4 P3 P2 Fig. 1 (7marks) PI (b) Redesign the circuit in (a) using a ROM. Show all your design steps. (4 marks) (c) Use the structural design style to write the VHDL code to describe the circuit in (a) if the entities of the FA and HA are as shown below. You are not required to write the VHDL descriptions of the FA and the HA. entity FA is port (a, b, ci: in std_logic; co, s: out std_logic); end FA; entity HA is port (a, b: in std_logic; c, s: out std_logic); end HA; (4 marks)