Figures 1 shows a 4-bit unsigned multiplication. Design a 4-bit variable- constant unsigned multiplier where the...

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Figures 1 shows a 4-bit unsigned multiplication. Design a 4-bit variable- constant unsigned multiplier where the constant input b = 13. Show all your design steps and draw the logic diagram using the minimum number of components. (a) %3D az a2 a, ao b3 b2 b bo azbo azbo a,bo aobo azb, azb, a,b aob, azb2 azb2 ab2 aob2 azb3 azb3 abs aob3 P7 P6 Ps P4 P3 P2 Po Fig. 1 (7marks) (b) Redesign the circuit in (a) using a ROM. Show all your design steps. (4 marks) Use the structural design style to write the VHDL code to describe the circuit in (a) if the entities of the FA and HA are as shown below. You are not required to write the VHDL descriptions of the FA and the HA. (c) entity HA is port ( a, b: in std_logic; c, s: out std_logic); end HA; entity FA is port ( a, b, ci: in std logic; co, s: out std logic); end FA; (4 marks) Figures 1 shows a 4-bit unsigned multiplication. Design a 4-bit variable- constant unsigned multiplier where the constant input b = 13. Show all your design steps and draw the logic diagram using the minimum number of components. (a) %3D az a2 a, ao b3 b2 b bo azbo azbo a,bo aobo azb, azb, a,b aob, azb2 azb2 ab2 aob2 azb3 azb3 abs aob3 P7 P6 Ps P4 P3 P2 Po Fig. 1 (7marks) (b) Redesign the circuit in (a) using a ROM. Show all your design steps. (4 marks) Use the structural design style to write the VHDL code to describe the circuit in (a) if the entities of the FA and HA are as shown below. You are not required to write the VHDL descriptions of the FA and the HA. (c) entity HA is port ( a, b: in std_logic; c, s: out std_logic); end HA; entity FA is port ( a, b, ci: in std logic; co, s: out std logic); end FA; (4 marks)

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Given that inpul b 13 to design a variable constant and we muliplier variable a Q a Qo and ... View the full answer