$($a$).$ Generate a pipelined implementation of the simple processor outlined in the figure that minimizes internal fragmentation. Each subblock in the diagram is a primitive unit that cannot be further partitioned into smaller ones. The original functionality must be maintained in the pipelined implementation. Show the diagram of your pipelined implementation. Pipeline registers have the following timing requirements: $($i$)0\mathrm{.}5-$ns setup time $($ii$)1-$ns delay time $($from clock to output$).($b$).$ Compute the latencies $($in nanoseconds$)$ of the instruction cycle of the nonpipelined and the pipelined implementations. $($c$).$ Compute the machine cycle times $($in nanoseconds$)$ of the nonpipelined and the pipelined implementations. $($d$).$ Compute the $($potential$)$ speedup of the pipelined implementation in problems $($a$)-($c$)$ over the original nonpipelined implementation. $($e$).$ What microarchitectural techniques could be used to further reduce the machine cycle time of pipelined designs? Explain how the machine cycle time is reduced. $($f$).$ Draw a simplified diagram of the pipeline stages in problem $($a$)$; should include all the necessary data forwarding paths. This diagram should be similar to Figure $2\mathrm{.}16.$