$($a$)$ Given the data path of a CPU as shown below:

Figure $1$: A simplified CPU

In the data path shown, the S$1,$ S$2$ and D fields in the instruction represent the two

source and one destination operands, and are directly connected to the address

port of the register file. Register S$1$ will be read into RFDUT$1,$ while register S$2$

will be read into RFQUT$2.$ RFIN will be written into register D$.$ Registers A and B

are the input registers and $C$ the output register of the ALU. There is a single

CPU bus in the data path.

Describe how the following instructions will be executed inside the CPU:

$($i$)$ The one$-$word instruction ADD R$1,$ R$2,$ R$3($i$.$e$.$ R$3$ R$1+$ R$2)[1]$

$($ii$)$ The $2-$word instruction, ADD DFF$1($R$1),($R$2),$ R$3[$i$.$c$.$ R$3$ larr OFF$1($R$1)+$

$($R$2)],$ where DFF$1($R$1)$ is the displacement addressing mode to specify the

memory address of the first source operands, DFF$1$ stored in the second word

of the instruction, and $($R$2)$ is the indirect mode. $[8]$

$($b$)($i$)$ What is the throughput of instruction execution for an ideal pipeline $($i$.$e$.$

number of instruction per clock cycle$).[2]$

$($ii$)$ Suggest one instruction that can cause the pipeline to stop and need to be

reinitialized. Explain why in one sentence. $[3]$