Given the data path of a CPU as shown below:

Figure $1$: A simplified CPU

In the data path shown, the S$1,$ S$2$ and D fields in the instruction represent the two

source and one destination operands, and are directly comnected to the address port

of the register file. Register $$1$ will be read into RFOU'T$1,$ while rogister $$2$ will be

resd into RFOUT$2.$ RFIN will be written into register D$.$ Registers A and $B$ ure the

input registers and $C$ is the output register of the ALU.

$($a$)$ Describe how the following instructions will be executed inside the CPU:

$($i$)$ The oneword instruction ADDR$1,R2,R3[$i$.$e$.R3$larrR$1+R2][3]$

$($ii$)$ T'he $3-$word instruction: ADDDFF$(R1),$ #IMGD, R$3$ i$.$e$.33$larrUFF$(R\mathrm{.}1)+$

#IMED$],$ where $)$ is the displacements addressing mode to specify the

memory address of the first sowre operand, and #IMMED is the immediate

mode for the second source operand, OFF stored in the second word of the

instruction, and ImMED slored in the third word. $[8]$

$($b$)$ A processor provides an instruction YovBLK which will move a string of bytes

from one memory location to another. Suppose the fetching and decoding of

the instruction takes $5$ clock cycles, and it takes $7$ cloc cycles to transfer each

byue, and the processor has a clock rate of $4GHz.$

$($i$)$ What is clock oycle time $($i$.$e$.$ The time for one clock cycle$)?[1].$

$($ii$)$ Determine the rumber of clock cycles needed to transfer a block of $64$ bytes,

ard hence the time rocuired to exccute this instruction. $[3]$

$($iii$)$ Waen will the processor usually check for interrupts? $[1]$

$($iv$)$ What is the problem with such a long executing instruction?

$($c$)($i$)$ What are the $3$ kinds of pipelime Lazard? Describe each of them in not

more two lines. $6]$

$($ii$)$ What pipeline hazard exist. for a branch instruction? Suggest one way t$.$c$.$

alleviale such pipeline hadzard. Give a short explanation. $[3]$