Question: A hypothetical computer system has a hierarchical memory architecture consists of cache memory of size 32 KB with a block size of 32 bytes.

A hypothetical computer system has a hierarchical memory architecture consists of cache memory of size 32 KB with a block size of 32 bytes. CPU generates 32-bit physical addresses. Identify the address structures for the following cache memory mapping functions. Direct Mapping (No. of bits required for Tag, Line and Word fields) Eight-way Set Associative Mapping (No. of bits required for Tag, Set, and Word fields)

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