A machine operates several instructions with MIPS pipeline. There are five pipeline stages in the MIPS

pipeline, including IF$,$ ID$,$ EX$,$ MEM, and WB$.$ We assume one clock cycle for each stage.

a$)$ How many clock cycles will be needed to complete $10$ instructions if the machine is non$-$pipelined?

b$)$ How many clock cycles will be needed to complete $10$ instructions if the machine uses $5-$stage MIPS

pipeline? Please list your assumptions explicitly.

c$)$ If the MIPS pipeline has K stages instead of $5,$ how many clock cycles will be needed to complete $n$

instructions? Please list your assumptions explicitly.