A Mcaly sequential circuit has one input (x) and one output (z). z1 if and only if the most recent input, combined with the preceding three inputs, was not a valid BCD encoding of a decimal digit; otherwise, z 0. Assume the BCD digits are received least significant bit first. Derive a state table for the circuit. Assume that in the reset state all previous inputs were 0. Three states are sufficicnt.) Next State 0 Previous 3 bits were-00 Previous 3 bits were Previous 3 bits were -10 Next State 0 Previous 3 bits were-00 l Previous 3 bits were - 0 Previous 3 bits were-10 0 Next State 0 Previous 3 bits were-00 Previous 3 bits were -10 Next State d. 0 Previous 3 bits were-00 l Previous 3 bits were 1 Previous 3 bits were -10 0