A microstrip circuit board with substrate thickness of b contains a fan-out that connects the output...

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A microstrip circuit board with substrate thickness of b contains a fan-out that connects the output of a logic gate on chip 0 to the input logic gates of two other chips, as illus- trated in the figure below: 100 Chip 1 width wi top view of PCB with dielectric E and depth h 211 & + D Zo width wo Chip 0 Uuu 2 The values of b and &, are fixed board parameters, and wo is also fixed for this problem. You may use the following approximations for the characteristic impedance and velocity of propagation on microstrip: 377 W 3 x 10⁰ D/2 width W₂ Jug 1 1 + 12b/w Chip 2 000 (a) Solve for the two trace widths w, and w, in terms of the parameters h, s, and wo in order to impedance match the circuit at the fan-out junction looking out of chip 0. (Ignore impedance discontinuities at the input of chips 1 and 2.) (b) Describe how you might design the widths ₁ and ₂ to obtain an impedance match looking out of chip 0 while simultaneously adjusting the propagation velocities so that signals from chip 0 arrive at the exact same time at chips 1 and 2. You do not have to solve for wy and w₂, but you should specify the conditions that Zo and up must satisfy. A microstrip circuit board with substrate thickness of b contains a fan-out that connects the output of a logic gate on chip 0 to the input logic gates of two other chips, as illus- trated in the figure below: 100 Chip 1 width wi top view of PCB with dielectric E and depth h 211 & + D Zo width wo Chip 0 Uuu 2 The values of b and &, are fixed board parameters, and wo is also fixed for this problem. You may use the following approximations for the characteristic impedance and velocity of propagation on microstrip: 377 W 3 x 10⁰ D/2 width W₂ Jug 1 1 + 12b/w Chip 2 000 (a) Solve for the two trace widths w, and w, in terms of the parameters h, s, and wo in order to impedance match the circuit at the fan-out junction looking out of chip 0. (Ignore impedance discontinuities at the input of chips 1 and 2.) (b) Describe how you might design the widths ₁ and ₂ to obtain an impedance match looking out of chip 0 while simultaneously adjusting the propagation velocities so that signals from chip 0 arrive at the exact same time at chips 1 and 2. You do not have to solve for wy and w₂, but you should specify the conditions that Zo and up must satisfy.