A NAND gate with eight inputs is required. For each of the following cases, minimize the number of gates used in the multiple$-$level result: $($a$)$ Design the $8-$input NAND gate using $2-$input NAND gates and NOT gates. $($b$)$ Design the $8-$input NAND gate using $2-$input NAND gates, $2-$input NOR gates, and NOT gates only if needed. $($c$)$ Compare the number of gates used in $($a$)$ and $($b$).$