A new processor design implements a $5-$stage pipeline $($Fetch$,$ Decode, Execute, Memory, Writeback$).$ Each stage performs its operation and then transfers data through pipeline registers to the next stage. The design team needs to analyze performance metrics for both pipelined and non$-$pipelined versions.

A processor design has the following stages and timing:

$-$ Fetch $($F$)$: Bns

$-$ Decode $($D$)$: $6$ ns

$-$ Execute $($E$)$: $12$ns

$-$ Memory $($M$)$; $10$ns

$-$ Writeback $($W$)$: $4$ ns

$-$ The pipeline registers between stages: $2$ ns delay each

system Requirements:

$-$ The processor must process $100$ instructions

$-$ The processor runs at a fixed clock rate

$-$ All instructions must go through all stages

$-$ The clock period must accommodate the slowest operation

$-$ Pipeline registers store data between stages at each clock cycle

$1.$ The clock period for an unpipelined version must be at least ns $($Add all stage delays$)$

$2.$ In the pipelined version with register delays, each cycle must be at least

ns $($Find longest stage $+$ register delay$)$

$3.$ To process $100$ instructions:

$1.$ Unpipelined total time: ns $($Consider unpipelined clock period$)$

$2.$ Pipelined total time: ns $($Consider pipelined cycle time$)$

$4.$ The speedup achieved through pipelining is

$($Unpipelined time $/$ Pipelined time$)($Give $3$ decimal points$)$