+ Expert Q&A D + 2. Assume a 5 stage pipeline - fetch, decode, execute, memory access and writeback. Let us say that you have no bypass logic to forward results to the ALU. Show cycle by cycle execution for the following code sequence and compute the total number of cycles to finish the last instruction after one iteration of the following code LOOP: LH R12, 10 (R11) SUBI R12, R12, 4 SH R12, 10 (R11) ADDI R11, R11, 4 SUB R14, R11, R13 BNEZ R14, LOOP 1. Assume a 5 stage pipeline-fetch, decode, execute, memory access and writeback. Let us say that you have bypass logic to forward results to the ALU from stages that may act as data source in the above-mentioned pipe stages. Show cycle by cycle execution for the following code sequence and compute the total number of cycles to finish the last instruction after one iteration of the following code. LI: LW R2, O(R1) ADDI R2, R2,2 SW R2, O(R1) ADDI R1, R1, 8 SUB R4, R1, R3 BNEZ R4, L1 + Expert Q&A D + 2. Assume a 5 stage pipeline - fetch, decode, execute, memory access and writeback. Let us say that you have no bypass logic to forward results to the ALU. Show cycle by cycle execution for the following code sequence and compute the total number of cycles to finish the last instruction after one iteration of the following code LOOP: LH R12, 10 (R11) SUBI R12, R12, 4 SH R12, 10 (R11) ADDI R11, R11, 4 SUB R14, R11, R13 BNEZ R14, LOOP 1. Assume a 5 stage pipeline-fetch, decode, execute, memory access and writeback. Let us say that you have bypass logic to forward results to the ALU from stages that may act as data source in the above-mentioned pipe stages. Show cycle by cycle execution for the following code sequence and compute the total number of cycles to finish the last instruction after one iteration of the following code. LI: LW R2, O(R1) ADDI R2, R2,2 SW R2, O(R1) ADDI R1, R1, 8 SUB R4, R1, R3 BNEZ R4, L1