A parallel adder is fast, but complex and high cost. Therefore, for some applications the speed is not of great importance, a cost$-$effective option is to use a serial adder, in which bits are added a pair at a time. Figure $1$ shows a block diagram of a serial adder. The serial adder can be implemented using an FSM as given in Figure $2.$ Write a Verilog code for the serial adder based on the FSM in Figure $2.$ In your design, it is suggested to use negative edge$-$triggered for the state register and positive edge$-$triggered for the shift register $($explain the reason in discussion$).$ Prove that your design is working by using ModelSim for simulation. In your report, please clearly explain the design flow $($i$.$e$.$ from specifications to verification processes$).$ Also, include detailed discussion of the results. Given A and B are $8-$bit size. Write Verilog HDL code for this Figure $///1.$ Write Verilog code HDL $2.$ testbench and attach picture Simulation waveform $8$bit as question required. Need write $2$ codes. Make sure the code is correct with Quart's prime and upload picture of the result and Simulation waveform $(8\_$bit$).$ Pls if u do not know the answer leave it to Somone can answer do not answer it wrong. becesue, I pay money to post this question.

Subject is Programmable Electronics