Question: A particular DMAC is using cycle - stealing to arbitrate for the bus. ( This is the strict version bellow with the declaration that unused

A particular DMAC is using cycle-stealing to arbitrate for the bus. (This is the strict version bellow with the declaration that unused Memory stages in the processor do not prevent the DMAC from using the bus.) If the CPU has asked for five words to be transferred by the DMAC and is in the middle of several ALU operations, how many total processor cycles does it take to complete the DMA operation? Show every step of your work.
add r1, r1, r2
sub r1, r6, r1
stw r1,0(r12)

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