A$)$ Phase lock loop problem: Assuming the PLL is locked and in steady$-$state condition with the input frequency $(20$ kHz $)$ seen on diagram. Identify frequency or frequencies at points $($a$),($b$)($c$),($d A DC or constant value would be recognized and denoted on answer line as zero frequency

At $($a$).$

AT $($b$)$

At $($c$).$

AT $($d$)$

Hz

Hz

A$)$ Phase lock loop problem: Assuming the PLL is locked and in steady$-$state condition with the input frequency $(20$ kHz $)$ seen on diagram. Identify frequency or frequencies at points $($a$),($b$)($c$),($d A DC or constant value would be recognized and denoted on answer line as zero frequency

At $($a$).$

AT $($b$)$

At $($c$).$

AT $($d$)$