A processor is equipped with an L$1$ I cache and with an L$1$ D cache. In a program P executing in this processor $20\%$ of the instructions are loads or stores, the miss rate for the D cache is $2\%.$ The latency to access memory is $150$ cycles. With a perfect cache, the CPI for this program is $1\mathrm{.}0$ and it would be $4$ times faster than the actual execution with cache misses. What is the miss rate of the L$1$ I cache?

Assume that L$1$D and L$1$I hit accesses occur in parallel.

For automated grading, express your answer as a percentage using one digit after the decimal and with no spaces, examples of acceptable formats for answers:

$25\mathrm{.}3$

$9\mathrm{.}3$

$2\mathrm{.}0$

$1\mathrm{.}7$