A program on a $5-$stage DLX pipeline executes $800,000$ instructions. Of these, $100,000$ are instructions that access data memory. For both the L$1$

I$-$cache and D$-$cache, the hit time is $1$ cycle, and the miss penalty is $10$ cycles. The hit rates for the I$-$cache and D$-$cache are $98\%$ and $92\%$ respectively.

Assume that all data and control hazards are resolved without any stalls or delays.