Question: A RISC processor has an eight stage pipeline: F D O E 1 E 2 MR MW WB ( fetch , decode, register read operands,

A RISC processor has an eight stage pipeline: F D O E1 E2 MR MW WB (fetch, decode, register read operands, execute 1, execute 2, memory read, memory write, result writeback to register). Simple logical and arithmetic operations are complete by the end of E1. Multiplication is complete by the end of E2. Assume that internal forwarding is possible and an operand can be used as soon as it is generated. Show the execution of the code:
LDR r0,[r2]
ADD r3,r0,r1
MUL r3,r3,r4
ADD r6,r5,r7
STR r3,[r2]
ADD r6,r5,r7

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