Consider the assembly code: I1: LOAD r3, M1 I2: LOAD r4, M2 I3: ADD r3, r4 I4: LOAD r4, M3 I5: ADD r4, r1 I6: MUL r3, r4 I7: LOAD r4, M4 I8: MUL r4, r2 I9: ADD r4, r3

written for a pipelined processor with pipeline stages: fetch, decode, register read, execute, write back. (a) i. Explain, with the use of a mathematical formula, what the program computes. ii. Identify the various addressing modes in the code. iii. Identify the true dependencies in the code.

(b) Find appropriate words/expressions to replace the numbers [n] so that the text below describes what happens when a load instruction is executed on a pipelined processor. For instance, the first replacement should be [1]=control. Note that different numbers may correspond to the same word/expression. The following text describes executing load instructions: The instruction has to be fetched and then to be decoded by the [1] unit of the CPU so that the addressing mode used to identify the [2] of the instruction is understood. If the instruction uses [3] addressing, then the next stage is [4], however, if [5] addressing is used then this stage can be skipped. In the latter case, data transfer between main memory and the CPU happens during the [6] stage: the CPU sends a [7] signal to main memory together with the address of the [8], the data is transferred via the bus and arrives into the [9] register. Finally, during the [10] stage the [11] is copied into the target register

(c) Identify those false dependencies in the code that can be removed by register renaming. (d) Rewrite the code by applying the register renaming technique. (e) Draw a diagram showing the execution of the code on a superscalar processor. You can assume that all the fetched and decoded instructions are already in the instruction window on the processor. There are two functional units for each of the remaining pipeline stages register read, execute, write back