A RISC processor is driven by a $2-$GHz clock. Instructions are executed in five$-$stage pipeline. Instruction statistics in a large program are as follows: Branch $10\%$ Load $40\%$ Store $20\%$ Computational Instructions $30\%$ Please answer the following questions. $($a$)$ Assume all memory access operations are cache hit. What is the ideal instruction throughput? $($b$)$ Assume there are an instruction cache and a data cache. For both caches, it takes $4$ cycles to complete the memory access if it is a cache miss. $80\%$ of instruction fetch are cache hit. $20\%$ are cache miss. For all Load instructions, the data to be accessed are in the data cache, but $30\%$ of the Load instructions are followed by a dependent instruction, which will stall the pipeline for one cycle. $40\%$ of the Store instructions store data into the data cache, while $60\%$ of them store data into the main memory. What is the instruction throughput? $($c$)$ Assume all memory accesses are cache hit. $40\%$ of the branch instructions are unconditional, while $60\%$ are conditional. $80\%$ of the conditional branches are taken, $20\%$ are not taken. The penalty for taking the branch is one cycle. What is the instruction throughput?