a. Suppose a non-pipelined processor requires 5 clock pulses to complete a register access instruction and 14 clock pulses to complete a memory access instruction. If this processor executes 200 register access instructions and 100 memory access instructions, how many clock pulses are required to complete these 300 instructions, and what will be the clocks per instruction (CPI) of these 30 instructions?

b. Consider the following two processors: a 5-stage pipelined processor where each stage completes in 1 clock pulse, and a non-pipelined processor where each instruction completes in 5 clock pulses. A single instruction requires 5 clock pulses to complete on either processor. Briefly explain how the use a pipeline offers a performance benefit.

c. Briefly explain how a pipeline can introduce Read After Write (RAW) hazards, and briefly explain how register forwarding may resolve RAW hazards in a pipeline.

d. Briefly describe what an atomic swap operation does and how it can be used to synchronize multiple processors.

e. Briefly explain how a write-invalidate protocol enforces cache coherence among multiple processors with shared memory.